Senior Digital IC Engineer — RTL Design & Verification
What you need
- 6+ yrs digital/mixed-signal ASIC RTL design through tapeout
- Strong SystemVerilog RTL and self-checking verification skills
- Hands-on synthesis, STA, and timing constraints experience
- Expertise in metastability, reset behavior, async interfaces
- Cross-discipline hardware-firmware/mixed-signal interface resolution
What you'll do
- Define requirements and interfaces with firmware/analog engineers
- Develop RTL for digital control and configuration logic
- Create verification plan, testbenches, assertions, regressions
- Own lint, CDC, synthesis, STA, timing constraints
- Deliver reproducible build-and-test flow and documentation
Visibl Semiconductors (YC W26) builds custom silicon for power electronics. Many hardware companies could benefit from chips designed around their products, but the cost and complexity of custom development put them out of reach. We’re working to change that.
We’re looking for a Senior Digital IC Engineer to own a substantial digital subsystem in an upcoming mixed-signal ASIC. You’ll work directly with our CTO, analog lead and customer firmware engineers, owning digital implementation, verification and synthesis handoff.
The job is more than writing RTL. We need someone who can understand the system around the chip, resolve unclear requirements with other engineers, and translate those decisions into hardware behavior we can verify.
What you’ll own
Requirements and interfaces. Work with firmware and analog engineers to clarify expected behavior, resolve assumptions and document interfaces. Turn those agreements into implementation requirements and verification tests.
Digital design. Develop and refine RTL for digital control and configuration logic. Make design tradeoffs explicit and raise integration risks early.
Verification. Develop a verification plan tied to requirements. Build self-checking testbenches, assertions and regressions covering normal operation, corner cases, resets and recovery. Use coverage to identify gaps, investigate failures and verify that fixes address their causes.
Implementation handoff. Own lint, clock/reset-domain crossing analysis, synthesis, timing constraints and static timing analysis. Deliver a reproducible build-and-test flow, clear integration documentation and an honest account of remaining dependencies.
Analog circuit design and full-chip physical implementation and signoff remain with the wider team.
What you bring
- Personal ownership of digital or mixed-signal ASIC work through RTL design, synthesis and tapeout, with direct involvement in validating the resulting silicon.
- Strong SystemVerilog RTL design and self-checking verification skills.
- Hands-on experience with synthesis, static timing analysis and timing constraints.
- Sound judgment around metastability, reset behavior and asynchronous interfaces.
- Experience resolving hardware–firmware or mixed-signal interface questions with engineers from other disciplines.
- The ability to work independently while communicating decisions, risks and verification results clearly.
Power-management ICs, mixed-signal integration and silicon bring-up experience are particularly relevant. FPGA experience is valuable alongside ASIC experience, but does not replace the tapeout and working-silicon requirement.
Working at Visibl
We’re a small, seed-funded team offering meaningful ownership and direct collaboration with the founders. Our CTO brings chip-design experience from Microsoft, Arm and Intel.
We believe great work comes from strong teams. We value people who communicate openly, support one another, and contribute positively to the way the team works together.
We use AI-assisted tools to accelerate implementation, debugging and verification, while keeping engineers responsible for design judgment and correctness.
Engagement and compensation
This is a paid, remote contract opportunity, with scope, weekly commitment and compensation agreed before starting. We’re prioritizing US-based candidates with regular overlap with our Pacific-time engineering team.
We’re also open to full-time employment. The displayed $160,000–$210,000 range is annual base salary for that option; contract compensation is agreed separately.
Please keep application responses non-confidential. We do not expect proprietary code or design details from previous employers.
Interview Process
We begin with a conversation with our CTO about your experience, including a chip you helped take to silicon and your specific contribution. A focused technical discussion follows on design, verification and interfaces. Please use non-confidential examples.
You’ll also meet our analog lead to discuss technical collaboration. The final conversation will be with our CEO to explore how your strengths and ambitions align with the company’s vision and growth.
Before an offer, we’ll agree on scope, compensation and availability. Any additional exercise will be explained in advance.
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About Visibl Semiconductors
Visibl makes custom chip development dramatically faster and lower cost for hardware companies. Today, most hardware companies that need a custom chip have bad options: sign a massive contract with an incumbent like Broadcom, pay a traditional design house millions of dollars and wait 18+ months, or keep using off-the-shelf chips and FPGAs that are not optimized for their product's cost, power, performance, size, or manufacturability. We handle the full path from architecture and design through verification, foundry management, and production. That makes custom ASICs accessible to robotics, drones, industrial, IoT, and edge hardware companies that were previously priced out of the market. As more hardware products need differentiated silicon, we think custom chip development should be available to far more companies than it is today.
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