The Tipping Point: Why Power Management Is the Next Battleground
Visibl Semiconductors, a three-person Y Combinator Winter 2026 company, signed a $250,000 SAFE on March 19. The shift is visible at the 63rd Design Automation Conference in Long Beach, where 15 AI-native EDA companies exhibited for the first time: Bronco AI, ChipAgents.ai, Normal Computing, Verkor.io, Silimate, Hu-mind, MooresLabAI, Visibl Semiconductors, Architect Labs, and others. They are not running demos. They are publishing production metrics: debug time cut from hours to minutes, autonomous flows handling full C-to-RTL-to-GDS pipelines, benchmarks built to measure AI performance in verification. Research Track submissions grew 26 percent year over year, Tech Times reported; the Engineering Track matched that pace. More than half the technical program addresses AI and design.
The market numbers explain why investors are paying attention. In the first quarter of 2026 alone, 80 semiconductor companies raised over $8 billion, Semiconductor Engineering found. Cyient Semiconductors closed a $30 million round from Edelweiss in May, VentureRadar's figures put it.
The hyperscalers proved the model. Google's TPU, AWS Trainium, and Microsoft Maia demonstrated that in-house silicon delivers differentiation at scale. But those programs required the resources of trillion-dollar companies. What changed is the infrastructure underneath: mature-node foundries with available capacity, AI-assisted design tools that compress verification cycles, and a venture ecosystem willing to fund the gap between specification and silicon.
The dirty secret of the semiconductor industry, as Visibl's founders put it, is that the thing most likely to blow up a chip program is not a physics problem. It is a document nobody updated after a meeting three months ago. When that gap reaches silicon, a respin costs $5 million to $20 million, StartupHub.ai found, and eats six to twelve months. The EDA incumbents, Synopsys and Cadence, together worth roughly $160 billion as StartupHub.ai reported, own the individual tools. The space between tools, where specification drifts from implementation and tests miss the gap, has been structurally underserved. AI-native coordination layers are targeting that space.
The Semiconductor Industry Association projects a shortage of 23,000 engineers by 2030. Demand for silicon is accelerating faster than the talent pipeline can fill. That scarcity makes the productivity gains from AI-assisted design not just attractive but necessary. The question at DAC 2026, framed by Simon Davidmann, co-creator of SystemVerilog and a six-time EDA founder, is whether these tools change what a team can verify, or merely how fast they run what they already verify. The answer will determine whether custom power management ASICs remain a hyperscaler luxury or become a standard option for any hardware company with a power problem worth solving.
Why the Economics Finally Make Sense
What changed is the cost side of the ledger.
For two decades, the economics of custom silicon were simple: if you weren't Apple, Google, or a hyperscaler, you couldn't afford the ticket. A 3nm tape-out carries $400–600 million in NRE. A 5nm design runs $200–400 million. Even 7nm sits at $100–200 million. Arm's 2023 IPO filing put the 28nm figure at roughly $48 million — still a stretch for a mid-sized hardware company. The mask set alone at 3nm exceeds $30 million; at 7nm it's ~$15 million. NRE breaks down to design and verification ($36M, 44%), photomasks ($25M, 31%), licensed IP ($12M, 15%), and EDA tools ($8M, 10%). A respin adds $5–20 million and six to twelve months.
| Process Node | NRE Range (M$) | Wafer Cost | Mask Set | Typical Use Case |
|---|---|---|---|---|
| 180–130nm | $0.4–3 | ~$3,000 | <$1M | Power management, MPW shuttles |
| 40–28nm | $3–20 | ~$5,000 | $2–5M | Mixed-signal, moderate volume |
| 7nm | $15–100 | ~$10,000 | ~$15M | High-performance, >100k units |
| 5nm | $30–200 | ~$16,000 | ~$25M | AI accelerators, hyperscalers |
| 3nm | $60–400+ | $19,500 | >$30M | Leading-edge compute only |
Moore's Law historically delivered both more transistors and lower cost per transistor. That equation broke at the 5nm node. TSMC 3nm wafers cost ~6.5× more than 28nm. Each EUV scanner runs $350M+. CoWoS advanced packaging lines are fully booked with 52–78 week allocation queues. The result: a 28nm chip's BOM might be $3–10, while a leading-edge AI chip's BOM is $3,000–$13,000 — a 1,000× increase driven by packaging and memory, not just silicon.
But power management doesn't need 3nm. It needs voltage regulation, sequencing, protection, and monitoring — analog and mixed-signal functions that map cleanly to mature nodes. At 180nm or 130nm, multi-project wafer (MPW) shuttles let teams share mask costs. Volume 10k–100k units: mature nodes with MPW. Volume >100k: full mask at 40nm, 28nm, or below often justified. The all-in cost per unit drops from $890 at 100k volume to $96 at 5M volume. A simple break-even model ($3M NRE divided by ($2.50 – $0.60) unit savings) yields roughly 1.58 million units, or ~19 months at 1M units annually before financing and taxes.
The economics didn't improve because advanced nodes got cheaper. They improved because the problem space, power management, never needed them in the first place.
AI-assisted design tools are compressing the largest cost bucket: verification. Design verification typically consumes >70% of chip project effort, Tech Times found. Bronco AI delivers root-cause analyses and suggested fixes in under 15 minutes with a 70% first-pass debug success rate, Tech Times reported. ChipAgents.ai reports PCIe root-cause analysis and patch in ~10 minutes versus four to eight hours of human effort. Verkor.io's Design Conductor constructed a Linux-capable RISC-V core in 12 hours. Visibl targets a roughly 90% reduction in engineering troubleshooting overhead, StartupHub.ai's figures put it, by detecting spec-implementation drift before it becomes a respin. At DAC 2026, >55% of the technical program focused on AI and design, Tech Times's data shows. Synopsys and Cadence, a $160B duopoly, have launched their own AI-EDA suites, though Simon Davidmann argues today's agentic EDA is largely a band-aid on legacy workflows, not a rethinking of the toolchain. The structural advantage remains with hyperscalers and large IDMs holding decades of proprietary design runs, verification outcomes, and layout data — no internet-scale corpus exists for semiconductor design the way it does for language.
The shift is already visible in team structures. Companies that once bought off-the-shelf PMICs from Texas Instruments or Infineon are now taping out custom ASICs at 28nm and 40nm, integrating four to eight discrete parts into one die, cutting BOM cost and board area. The talent implications are next.
The New Design Partners: AI-Native EDA Startups
Y Combinator's Winter 2026 batch included Visibl Semiconductors, founded in 2024 by Jordon Kashanchi and Bryce Neil. Kashanchi, CTO, designed digital logic and microarchitecture for next-gen custom AI silicon at Microsoft after stints at Arm and Intel; he holds an MS in ECE from UT Austin and is published in PNAS and ACM. Neil, CEO, built production software and data systems for Deloitte's OmniaAI team, healthcare, and the public sector; his work has run in leading U.S. hospitals. They frame the problem as coordination, not physics: specifications, RTL, and verification tests live in disconnected tools and drift out of sync across thousands of engineering hours. That gap reaching silicon necessitates a costly respin.
Visibl's agents monitor specs, implementation, CI logs, and design collateral to detect drift early, create cases with evidence, propose fixes, run verification, and package review-ready diffs, gated by human approval. The claimed impact: a similar reduction in engineering troubleshooting overhead, 10x less triage, and avoided late-stage surprises that lead to $10M+ respins. The company manages the full path from architecture through fabrication, packaging, and production-ready silicon so hardware teams do not need an in-house chip team. Its initial verticals: data-center and AI-infrastructure power, motor drives, industrial automation and robotics, battery systems and e-mobility powertrains, EV charging, solar, energy storage, grid power, HVAC, heat pumps, and appliances.
Visibl is not alone. Bronco AI, at Booth 935, unveiled a production-grade benchmark for design verification AI: an agentic architecture that autonomously produces similar metrics. ChipAgents.ai reported a similar PCIe analysis in roughly 10 minutes. Verkor.io's Design Conductor platform achieved a similar feat in 12 hours. All three shared floor space at DAC 2026 with Cadence, Synopsys, and Siemens.
The venture logic is straightforward: custom silicon has long been a rich company's game, with design projects that run for years and swallow tens of millions of dollars. Data-center operators, edge device makers, and automotive suppliers increasingly want silicon tailored to their workloads instead of off-the-shelf parts. If AI agents can shrink the timeline, a wider range of teams can afford chips designed around their exact needs, opening a bigger market for the custom silicon ecosystem. The EDA market is projected to reach $23.9 billion by 2030, StartupHub.ai's data shows.
Incumbents are not standing still. Synopsys has launched its AI-EDA suite under the Synopsys.ai brand. Cadence has similar initiatives. But there is a structural difference between bolting AI onto tools designed in the 1990s and building an AI-native coordination layer from scratch. Synopsys's AI features make individual tools smarter. Visibl's bet is that the actual problem is between the tools, not inside them. Davidmann frames the tension as "Davidmann's Test": does an AI tool change that, or merely speed up current verification? By that measure, he argues, it's largely the same band-aid approach, not a fundamental rethink.
The training data bottleneck looms over every AI-native EDA claim. There is no publicly available, internet-scale corpus of semiconductor design data the way there is for language or images. The teams with such proprietary data, the hyperscalers and large IDMs quietly building their own AI stacks, hold an architectural advantage that no off-the-shelf model can easily replicate. Columbia University's Luca Carloni argues that open-source hardware platforms may provide the shared artifacts needed for genuine agentic AI workflows. Visibl's on-premises deployment model creates switching costs that cloud-native SaaS products do not have; once integrated into a chip team's CI pipeline and EDA toolchain, ripping it out is a significant undertaking. The data flywheel gets meaningfully better with each customer, and each customer makes it harder for a new entrant to compete on model quality.
The semiconductor industry tends to move slowly on toolchain adoption. When it moves, it tends to move all at once. The question is whether Visibl and its peers can land enough early customers to escape velocity before a well-resourced incumbent decides to build the same thing from scratch. Given where Synopsys and Cadence are focused, making their existing tools smarter rather than solving cross-tool coordination, they have a credible window.
How Established Chip Giants Are Responding
Texas Instruments is not waiting for the custom ASIC wave to break on its doorstep. In 2024, while the broader semiconductor market softened and revenue fell 11% to $15.6 billion, TI plowed $4.8 billion into capital expenditures — nearly a third of its top line. The explicit goal: expand internal 300mm wafer fabrication capacity so that by 2030 more than 95% of its wafers are sourced internally, with over 80% on the cost-advantaged 300mm platform. The company reports it is already roughly 70% through that CapEx cycle. A 300mm wafer yields a structural cost advantage of approximately 40% per chip compared with the 200mm wafers many analog competitors still rely on. That manufacturing moat is the foundation of TI's counter-move.
The strategy is a flywheel. Financial fortitude ($6.3 billion in cash flow from operations in 2024, free cash flow actually up 11% to $1.5 billion) funds the manufacturing build-out. The 300mm capacity lowers unit cost and secures supply-chain independence, a selling point in an era of "China-Plus-One" sourcing mandates. That cost advantage lets TI price its Edge AI processors and the crucial accompanying analog chips more aggressively than fabless rivals beholden to foundry queues and pricing. The output is a portfolio of over 80,000 products spanning power management, signal chain, and embedded processing. In 2024, analog products generated roughly 78% of revenue and proved resilient, declining only 7% versus a 25% drop in the more cyclical Embedded Processing segment. Industrial and automotive markets together accounted for about 70% of revenue.
TI's "component moat" is the strategic linchpin. Even when a customer selects an AI processor from NXP, Renesas, or a custom ASIC, they are highly likely to design in TI's high-margin power management and signal-chain chips to make the system function. Nvidia's most advanced AI supercomputers rely on TI analog chips for power regulation. That position lets TI profit from the growth of the entire Edge AI market, not just the slice captured by its own processors. The Edge AI market, fragmented across tens of thousands of customers in factory automation, robotics, automotive, and smart infrastructure, plays to TI's historical strength: a massive, diverse customer base served through a distribution model built for breadth, not just a handful of hyperscalers.
The hardware response centers on heterogeneous SoCs that integrate AI acceleration with the analog and real-time control functions TI already dominates. The Jacinto line for automotive (ADAS, digital cockpit, domain controllers) and the Sitara line for industrial (robotics, machine vision, HMI) both employ a C7x DSP core with a dedicated Matrix Multiply Accelerator (512-bit vector processing plus scalar CPU) delivering up to 32 TOPS on the flagship TDA4VH-Q1. The AM62 family brings AI to sub-$5 volume pricing with active power under 1.5 W and suspend states as low as 7 mW. Critically, these processors integrate safety MCUs (lockstep Cortex-R5F cores) and power management on the same die, reducing BOM count and board complexity — the very integration value proposition that custom ASIC startups pitch.
The software response is Edge AI Studio: Model Composer (no-code/low-code GUI for data annotation, training, compilation, and deployment), Model Analyzer (free cloud access to real evaluation hardware), a growing Model Zoo of pre-trained models, and TIDL runtime for efficient execution across heterogeneous cores. The stack supports TensorFlow Lite, PyTorch, ONNX, and GStreamer. TI's aim is to unlock the vast base of embedded developers who know C and RTOS but not Python or TensorFlow, making its silicon sticky before a custom ASIC effort can get off the ground.
The competitive map is sharpening. Monolithic Power Systems (MPS) operates a "fabless-lite" model, with proprietary BCD process technologies installed on foundry partners' equipment, and has won high-volume GPU sockets with 48V multiphase regulators, posting 55–60% gross margins and revenue growth from $2.21 billion (2024) to $2.80 billion (2025), with analysts projecting $3.39 billion for 2026. Vicor, with its Vertical Power Delivery modules, reported a book-to-bill above 2 in Q1 2026 and a $300 million backlog, but remains capacity-constrained. Analog Devices competes on high-precision signal chains in premium segments. NXP's i.MX 8M Plus (2.3 TOPS NPU) targets Sitara; STMicroelectronics is embedding AI into its ubiquitous STM32 MCU line; Renesas's R-Car V4H (34 TOPS) goes head-to-head with Jacinto in automotive.
For the custom ASIC thesis, the incumbents' response raises the bar. TI is not ceding the integration argument — it is integrating more functions per die, at lower cost, with a software stack that shrinks the time-to-advantage a custom ASIC must overcome. MPS and Vicor are proving that specialized power architectures (48V, vertical delivery) can win high-volume AI sockets without full custom ASICs. The window for a startup to sell "integration alone" is narrowing; the differentiator must be a power topology or control algorithm the incumbents cannot or will not productize for a fragmented market. The giants are not standing still — they are widening the moat.
How Power Electronics Teams Are Rewiring Their Design Process
The move from selecting a PMIC from a TI or Infineon catalog to taping out a custom power-management ASIC does more than change a bill of materials. It rewires the engineering organization. A mixed-signal ASIC combines analogue circuits that sense voltage, current, and temperature with digital logic that sequences rails, manages faults, and communicates with a host processor — all on one die. Swindon Silicon, which has delivered mixed-signal ASICs into automotive, industrial, and aerospace programs for over four decades, classifies this work into three categories: sensor interface and signal conditioning, power management and regulation, and data conversion and high-speed signal processing. Power management ASICs sit at the intersection of the first two, and the research shows that the critical requirement is co-designing the power blocks with the signal-conditioning circuitry to keep the noise floor acceptable across the operating range.
That co-design requirement is where most teams hit the wall. High-speed digital switching generates sharp current transients that propagate through shared supply rails and substrate into ADC inputs and amplifier stages. Experienced mixed-signal designers manage this through physical partitioning of the two domains, separate supply routing, and careful floorplanning of the analogue front-end relative to the digital core, a layout discipline as much as a circuit-design one. Analogue circuits also do not behave consistently across process corners or temperature; an automotive sensor-interface ASIC must hold accuracy from minus 40 to plus 150 degrees Celsius across natural transistor variation from wafer to wafer. Thorough simulation across all process, voltage, and temperature corners is essential before tapeout, and designing the right margin at the circuit level is a skill that comes from real silicon, not simulation alone.
Calibration adds another layer. Precision mixed-signal ASICs in sensing applications typically require individual trim during production test, where each device is measured and correction values are programmed into non-volatile memory. Designing that calibration architecture and the test process that applies it efficiently at volume directly affects die area, test time, and yield. It is most effective when planned from the start, not bolted on late. Qualification compounds the complexity: automotive and aerospace ASICs must pass AEC-Q100 accelerated lifetime testing, temperature cycling, humidity stress, and ESD validation, while safety-critical programs add ISO 26262 functional-safety requirements. Planning qualification in parallel with design, rather than treating it as a final step, avoids costly late-stage redesigns.
The organizational response is visible in hiring and partnerships. Cyient Semiconductors acquired a majority stake in Kinetic Technologies in December 2025 specifically to combine Kinetic's power-management and protection IC depth with Cyient's custom ASIC engine, targeting Edge AI and high-performance compute markets. CEO Suman Narayan said the combination would "shorten development cycles and scale our ability to solve the toughest power, thermal, and reliability problems in high volume systems." Both models, acquisition and AI-assisted design partnership, reflect the same pressure: power electronics teams need mixed-signal expertise they don't have in-house, and they need it earlier in the program.
Tooling is shifting to meet that pressure. The EDA market, valued at $14.55 billion in 2025 and projected to reach $34.71 billion by 2035, is embedding generative AI and agent-based automation into layout optimization, verification, and workflow orchestration. Synopsys announced its Multiphysics Fusion portfolio in June 2026, unifying EDA with Ansys golden-signoff analysis across timing, design closure, multi-die, and analog workflows — delivering up to 10x faster design closure and SPICE-accurate multiphysics timing analysis. For power-management ASICs, where thermal, electromagnetic, and power-integrity effects are inseparable, that convergence matters. Cadence's Amol Borkar noted that machine learning can help with mixed-signal co-design by automatically tuning DSP algorithms based on analog simulation data, reducing cycles and helping engineers balance analog precision against DSP complexity.
The net effect: a power electronics team that once specified a PMIC, laid out a PCB, and wrote firmware now defines a mixed-signal architecture, partitions analog and digital domains, plans calibration and test, runs multiphysics signoff, and coordinates qualification — all before first silicon. The next hire isn't a PCB layout engineer. It's a mixed-signal ASIC designer who has taken a power-management chip through AEC-Q100.
The Talent Crunch: Why Every Hardware Company Is Hiring Chip Designers
The numbers are stark. Deloitte forecasts a global deficit of more than one million skilled semiconductor workers by 2030. McKinsey projects a sizable U.S. engineering and technician gap by 2029. A July 2026 study from McKinsey, SEMI, and the National Science Foundation puts the U.S. shortfall at up to 157,000 full-time equivalents by 2030, with engineers accounting for roughly 60 percent of unmet demand, about 83,000 to 88,000 roles. Seventy-three percent of employers already report significant difficulty hiring engineers, per the same survey. The National Network for Microelectronics Education's 2026 landscape analysis projects cumulative incremental demand of roughly 189,000 FTEs between 2026 and 2030 across announced fab investments and baseline replacement needs, including approximately 104,000 engineers, 73,000 technicians, and 12,000 computer scientists. Only about 3 percent of engineering graduates enter the semiconductor industry. Most choose software and AI.
This is not a cyclical dip. Talent scarcity is structural, driven by fab buildouts outpacing education capacity, an aging workforce, and competition from cloud providers and AI hardware companies chasing the same verification, architecture, and silicon-systems talent. Location friction persists even with hybrid work. The deficit concentrates in roles on the critical path: mixed-signal design, physical implementation, low-power signoff, and design-for-test.
For power management ASICs specifically, the squeeze is tighter. Analog IC design engineers — the people who balance efficiency against quiescent current, manage thermal performance, and ensure robust operation across varying loads — command premium compensation. Glassdoor's 2026 data shows average base pay of $183,382 for Analog IC Design Engineers (25th–75th percentile: $149,211–$228,599) and $199,249 for Analog IC Designers (25th–75th: $156,825–$257,207). Top earners clear $277,000 and $320,000 respectively. Advanced-node ASIC specialists bill $120–$190 per hour on contract. FPGA contractors run 15–25 percent above comparable ASIC roles.
A single missed clock-domain-crossing bug or sub-optimal timing path can cost millions in respin expenses and delay a roadmap by two quarters.
Design verification consumes more than 70 percent of chip project effort, a bottleneck the field has struggled to automate for decades.
Companies are responding in three ways. First, compensation structures are shifting toward scarcity: equity tied to program milestones, 90-day ramp plans, and bands that reflect velocity, not just tenure. Second, startups and mid-sized firms are hiring fractional principal architects and verification leads through platforms like AnySilicon, which connects teams with pre-vetted RTL architects, SoC specialists, and turnkey design houses. Third, AI-assisted design tools are entering the loop — Bronco AI delivers similar metrics; ChipAgents.ai cuts PCIe debug from hours to roughly ten minutes; Verkor.io achieved a similar feat in twelve hours using agentic EDA. Google has taped out data-center silicon on an agent-driven stack. These tools don't replace engineers; they amplify the few you can hire.
The implication for frontier-tech verticals is direct. Robotics companies building custom motor-drive ASICs, defense contractors hardening power supplies for avionics, energy startups integrating wide-bandgap switches — all of them now compete for the same analog-mixed-signal talent pool that hyperscalers and AI-chip ventures are draining. The winning play isn't outbidding Nvidia. It's structuring roles to match the real bottleneck, mapping adjacency talent from adjacent IP blocks, and running compressed assessments centered on work simulation rather than resume keywords.
Watch the technician gap next. Employer-linked quick-start programs and apprenticeships achieve 70–90 percent placement and scale faster than four-year degrees. The NNME analysis shows technician gaps of 38,000–63,000 FTEs depending on CHIPS-funded program effectiveness. If you're building a custom power ASIC team, your first hire might not be a PhD — it might be a technician who can run the lab while your senior designer closes timing.
What to Watch Next
This article has tracked a specific inflection point: custom ASICs for power management are becoming accessible to hardware companies that never considered silicon design five years ago. The drivers are mature-node foundries (180 nm down to 28 nm), AI-assisted analog layout tools, and a wave of YC-backed startups like Visibl Semiconductors that compress NRE and timeline. That story is about mixed-signal integration on established processes: PMICs that replace discrete FETs, controllers, and passives in robots, satellites, EV chargers, and defense power supplies.
Three adjacent stories are not this one.
First, advanced-node AI compute ASICs. Broadcom and Marvell together control roughly 95 percent of that co-design market. Broadcom guided $58 billion in AI revenue for fiscal 2026 and targets more than $100 billion in 2027. Marvell projects up to $11 billion in custom AI ASIC revenue for 2026. TSMC's 3 nm node hit roughly 150,000 wafers per month by end-2025 and aims for 180,000–200,000 by end-2026. The custom AI ASIC market is projected to grow from $9.25 billion in 2025 to $68.4 billion by 2032 at 33 percent CAGR. All five hyperscalers are slated to ship more than 10 million custom AI chips annually by 2027. That is a capital-intensive, digital-dominant, leading-node race. It shares the phrase "custom silicon" but not the economics, the process nodes, the design flows, or the customer base. A robotics company building a 48 V motor-drive ASIC on 180 nm has almost nothing in common with a hyperscaler co-designing a 3 nm TPU with Broadcom.
Second, digital-only custom processors. The research documents RISC-V core startups, AI inference accelerators from Tenstorrent, Groq, Sambanova, Cerebras, and Positron, and CPU efforts from Qualcomm (Dragonfly) and AMD (Instinct MI400/MI500 series). These are logic-heavy, memory-bound, compiler-dependent designs. Their pain points are software stacks, CUDA compatibility, and HBM integration — not analog floorplanning, voltage-domain isolation, or thermal co-simulation with magnetics. The talent pools barely overlap. The analog/mixed-signal engineers who design a buck-converter ASIC on 130 nm are not the same people writing RTL for a tensor core.
Third, foundry manufacturing expansions. TSMC's $44.96 billion capital allocation in February 2026, its Arizona/Japan/Germany fabs coming online 2027–2028, the CoWoS-L capacity crunch, and the substrate bottleneck at Unimicron all matter for advanced-node AI chips. They do not gate mature-node power ASICs. GlobalFoundries, Tower, TSMC's 28 nm/40 nm/180 nm lines, and the specialty foundries (X-Fab, Vanguard, PSMC) have ample capacity for the volumes this article describes. The constraint for power-management ASICs is design talent and IP reuse, not wafer allocation.
What to watch next.
Watch the analog EDA layer. Cadence and Synopsys are embedding AI-assisted layout for analog blocks — not just digital place-and-route. If those tools deliver 30–50 percent cycle-time reduction on mixed-signal blocks, the NRE floor drops another rung. Visibl's claim of cutting ASIC development cost and timeline on mature nodes will be tested against real tape-outs in 2026–2027.
Watch the incumbent response. Texas Instruments, Analog Devices, Infineon, and Onsemi still own the PMIC catalog. They have started offering semi-custom variants and reference designs that blur the line between "buy" and "build." If they open their IP libraries to third-party integration (say, a TI buck controller hardened into a customer's ASIC), the economics shift again.
Watch the talent market. The research shows ASML adding 79 roles in a week, Stripe 56. But those are not analog/mixed-signal roles. The board data for analog ASIC houses is thinner. Universities are not graduating more. The companies that secure pipeline through co-op programs, internal training, or acqui-hires will ship first.
Watch the packaging intersection. Power ASICs increasingly need integrated magnetics, high-voltage isolation, or chiplet-style stacking with SiC/GaN FETs. OSATs like ASE (VIPack) and Amkor are developing fan-out and 2.5D flows for power density, not just HBM bandwidth. The first company to standardize a "power chiplet" interface (think UCIe but for 48 V/800 V domains) creates a new supply chain tier.
Watch the defense and energy procurement signals. The CHIPS Act's $39 billion in incentives includes mature-node capacity. If DoD and DOE start writing "custom ASIC" into power-electronics requirements for radar, satellite bus, or grid-tie inverters, the volume floor rises fast.
The wall didn't just crack. It fell.
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