Founding ASIC Engineer (Architecture & RTL)

This is a hands-on role with substantial influence over our first chip, our engineering process, and the team we build. We're looking for someone who has built real chips and understands the practical challenges of taking a design from architecture through implementation, tapeout, and silicon validation.

What you'll own

• Develop the chip architecture and microarchitecture with the founders, making explicit trade-offs across model quality, latency, throughput, power, and area.
• Design compute datapaths, low-precision arithmetic units, weight-storage structures, SRAM/KV-cache systems, scheduling, and on-chip data movement.
• Write, review, and optimise synthesizable RTL in Verilog or SystemVerilog, including critically evaluating generated hardware where useful.
• Develop a robust verification strategy using software reference models, simulation, assertions, and formal methods where appropriate.
• Use synthesis, static timing analysis, and representative physical implementation experiments to assess feasibility and identify problems early.
• Make implementation-aware design decisions around timing, congestion, power, memory macros, and physical constraints.
• Help define implementation requirements and evaluate external physical-design, IP, and foundry partners.
• Work with external partners through physical implementation, tapeout preparation, and silicon bring-up.
• Establish our hardware development workflows, tools, verification infrastructure, and engineering standards.
• Help recruit and mentor future hardware engineers as the team grows.

What we're looking for

• Strong hands-on digital ASIC design experience, including personal ownership of a substantial block or subsystem through tapeout and validation of the resulting silicon.
• Excellent Verilog/SystemVerilog skills (and/or XLS) and experience developing complex, synthesizable RTL.
• Strong functional verification skills, including testbench development, simulation, debugging, and verification against reference models.
• Practical understanding of synthesis, static timing analysis, power, area, and physical-design constraints.
• Experience designing compute datapaths, memory systems, or other performance-critical digital logic.
• The engineering judgment to recognise when an architecturally elegant design will create problems during implementation.
• Ability to translate incomplete requirements into clear specifications, robust designs, tests, and engineering decisions.
• Comfort working across architecture, RTL, verification, implementation, and debugging rather than staying within a narrow specialism.
• Willingness to take substantial technical ownership and work directly with two founders in an early-stage environment.
• Comfort using AI tools to accelerate development, verification, and engineering workflows.

Especially useful experience

• AI accelerators, NPUs, GPUs, CPUs, or other compute-intensive ASICs.
• Low-precision arithmetic, including binary or ternary compute.
• SRAM/ROM integration, memory macros, or on-chip memory architectures.
• Hardware–software co-design and FPGA-to-ASIC development.
• EDA tools from Synopsys, Cadence, or Siemens.
• Working with external ASIC design houses, physical-design teams, or semiconductor foundries.
• HLS or hardware generation frameworks such as XLS or Chisel.

Prior experience with binary or ternary LLMs is welcome, but not required. Strong hardware fundamentals, practical silicon experience, and the ability to learn new workloads matter more.

Why join

You'll help build a new approach to AI inference hardware from its earliest stage.

This is an opportunity to own meaningful parts of an entire chip, rather than a small component of a mature semiconductor programme.

You'll work directly with the founders and architecture researchers, shaping technical decisions from the earliest design concepts through to manufactured silicon.

You'll also help establish the engineering foundations of the company: our design methodology, verification standards, development tools, implementation partnerships, and future hardware team.

We're looking for someone who enjoys solving difficult technical problems, takes pride in building hardware that works, and wants to help create something from the ground up.

We're currently based in San Francisco and London.