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Senior ASIC Design Verification Engineer
Posted 1 year ago• Avionics
Compensation
$120,000–$210,000/year
Job Description
Senior ASIC Design Verification Engineer at Velaura AI. Location: Santa Clara, California. Salary: USD 120,000-210,000/year. Seniority: Senior. Experience: 15+ years. Skills: Project Execution, C/C++, UVM, PCIe, Scenario Testing, Quality Assurance, Scripting, Register Transfer Level, SystemVerilog, Artificial Intelligence, ASIC, Functional Verification, Ethernet, Python, Hardware Engineer.
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Job Details
- Category
- Avionics
- Employment Type
- Full Time
- Location
- Santa Clara, California
- Posted
- Mar 28, 2025, 03:51 PM
- Listed
- Apr 4, 2026, 05:24 PM
- Last updated
- Apr 4, 2026, 10:50 PM
- Compensation
- $120,000 - $210,000 per year
About Velaura AI
Part of the growing space & AI ecosystem pushing the frontiers of technology.
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Senior ASIC Design Verification Engineer
Velaura AI
