Junior RTL design engineer – AI Networking

Junior RTL design engineer – AI Networking at Velaura AI. Location: Santa Clara, California. Salary: USD 65,000-205,000/year. Seniority: Mid. Experience: 5+ years. Skills: UVM, Physical Design, Static Timing Analysis, Scripting, Register Transfer Level, Artificial Intelligence, ASIC, Integrated Circuit Design, Modeling, Logic Design, GPU, Networking Technologies, Timing Closure, Python, Hardware Engineer.