<candidate>ASML's Backlog Hit €38.8 Billion. The Bottleneck Isn't Machines — It's the PLM Engineers and IT Architects Who Wire Them Together</candidate>
Inside SpaceX's Terafab Gamble
On March 21, 2026, Elon Musk stood inside Austin's decommissioned Seaholm Power Plant and announced what may be the most audacious infrastructure project in semiconductor history. Terafab, a joint venture between Tesla, SpaceX, and xAI, aims to produce one terawatt of AI compute per year from a facility complex in Texas. That target represents roughly half the total computing capacity currently generated across the entire United States, Musk said.
A typical advanced chip fabrication plant costs north of $20 billion and takes years to build. Terafab's initial phase carries a $25 billion price tag, with the full-scale Grimes County facility estimated at $55 billion for the initial phase and up to $119 billion across all phases. At full build-out, the factory is expected to cover up to 10 million square meters, making it one of the largest industrial facilities on Earth, with a target of one million wafer starts per month. By comparison, TSMC, the world's dominant foundry, produces about 16.8 million wafers per month across its entire global network of fabs spanning multiple countries.
"We either build the Terafab or we don't have the chips," Musk said during the Austin presentation. He claimed existing global fab output covers only 2% of what his companies need. The chips in question fall into two categories: energy-efficient inference processors for Tesla's Full Self-Driving systems, Cybercab robotaxi fleet, and Optimus humanoid robot; and radiation-hardened, high-power processors designed to operate aboard SpaceX satellites and xAI's planned orbital data centers (chips that must function at higher temperatures and withstand the particle radiation of low-Earth orbit).
Neither Tesla nor SpaceX has ever operated a semiconductor fabrication facility. That gap is the reason Intel exists in this story. On April 7, 2026, Intel announced it would serve as Terafab's primary foundry partner, bringing five decades of processor design expertise, advanced packaging technologies like Foveros 3D stacking, and fabrication infrastructure already under expansion with $8.5 billion in CHIPS Act funding. Intel's stock jumped more than 3% on the news, trading at $52.28 by early afternoon, its strongest single-session performance in months. For Intel CEO Lip-Bu Tan, who has staked his turnaround strategy on transforming Intel into a viable contract chipmaker, Terafab represents the anchor customer that could finally justify the massive capital expenditures behind Intel Foundry Services.
Tesla is leading the prototype fab at its existing Giga Texas site, targeting 2nm process technology and an initial output that Musk later revised to "maybe a few thousand wafers per month" for the pilot phase, intended primarily to iterate on chip designs without shipping wafers between facilities. SpaceX is leading the full-scale Grimes County build-out. Intel provides the manufacturing backbone.
ASML CEO Christophe Fouquet confirmed direct talks with Musk about supplying lithography equipment for the project, calling Musk "very serious," but issued a pointed caveat: Terafab only works as an opportunity if ASML doesn't run out of machines to sell. With EUV lithography backlogs at record levels and each High-NA EUV system costing approximately $380 million, ASML's supply capacity is itself a bottleneck that could shape Terafab's timeline as decisively as any engineering challenge.
The prototype facility at Giga Texas is expected to begin small-batch production of Tesla's AI5 chip in 2026, with volume production targeted for 2027. The full-scale Grimes County fab, for which county commissioners approved a property tax abatement package on June 3, 2026, has no confirmed production date, though analysts have noted that even optimistic scenarios place initial output no earlier than late 2028, with high-volume manufacturing ramping through 2029.
ASML's Quiet Staffing Blitz
While Musk's Terafab announcement grabbed headlines, ASML has been staffing up to meet the demand that project, and the broader AI chip boom, is creating. The company's careers page shows 48 roles added in the past week alone, spanning customer support, manufacturing engineering, and technical training positions across the US, Taiwan, and the Netherlands.
The hiring push is global but concentrated in specific hubs. In San Diego, ASML is recruiting manufacturing engineers and test engineers for its US operations. In Taiwan, where TSMC, ASML's single largest customer, operates its most advanced fabs, the company is hiring EUV customer support engineers and SAP coordinators in Kaohsiung and Tainan. These are the people who keep ASML's lithography scanners running at customer sites, a role that grows more critical as the installed base expands.
A modern leading-edge logic fab needs between 80 and 100 lithography scanners to support 20,000 to 30,000 wafer starts per month. At the scale Musk has described, a $55 billion facility targeting 2nm-class production using Intel's 14A process, the equipment procurement pipeline represents a potential multi-billion-dollar order stream for ASML.
ASML's order backlog already stands at €38.8 billion, a figure that reflects demand years into the future. JPMorgan analyst Sandeep Deshpande raised his price target to €1,900 in June, arguing ASML can deliver more than 110 low-NA EUV systems annually without adding new building space, well above the roughly 90-unit ceiling the market had assumed. Morgan Stanley separately raised its target to €1,660, citing ASML's planned expansion at the Brainport Industries Campus in Eindhoven, with construction set to begin in Q3 2026.
The hiring isn't without friction. ASML announced plans to cut about 1,700 jobs in the Netherlands as it streamlines tech and IT units. The company is simultaneously trimming in some areas while expanding in others, a rebalancing toward customer-facing and manufacturing roles tied directly to EUV output growth.
The June 11–12 virtual fireside chat between Musk and Fouquet at ASML's annual technology conference in Den Bosch underscores how central this relationship has become. The event has not been universally welcomed inside the company (some employees announced plans to boycott the session on inclusivity grounds, according to Eindhovens Dagblad), but ASML defended the invitation on industrial grounds.
For engineers watching the semiconductor space, the signal is clear: ASML is hiring where the machines go, and the machines are going everywhere. Taiwan, the US, and the Netherlands remain the three pillars of that expansion.
What the Roles Reveal: PLM and IT at the Core
The Terafab project is, at its foundation, a software problem disguised as a construction project. Building a facility that covers up to 10 million square meters and integrating every stage of semiconductor production under one roof demands a digital backbone that most companies have never attempted to build. That backbone runs on product lifecycle management systems, IT infrastructure, and automation engineering, and the roles ASML is hiring for reveal just how much of the challenge lives in code and data rather than concrete and steel.
ASML's careers page lists openings across more than 60 global locations, with the heaviest concentration in the Netherlands, where the company's Veldhoven headquarters houses more than half of its roughly 42,000 employees. The roles most relevant to a project like Terafab fall into three overlapping categories: PLM engineers who manage the digital thread from chip design through fabrication, IT systems integration architects who connect lithography tools to factory-wide data networks, and automation specialists who build the material handling and process control systems that keep wafers moving through a fab without human hands touching them.
PLM is the discipline most people outside the semiconductor industry have never heard of, and it is arguably the single most critical function in a vertically integrated fab. In a conventional chip supply chain, design happens at one company, mask sets at another, fabrication at a foundry, packaging at a third party, and testing somewhere else. Each handoff introduces data translation errors, version mismatches, and delays. Terafab's entire premise, "make a chip, test it, revise the mask, and repeat without shipping wafers between sites," collapses those handoffs into a single facility. That collapse only works if every team, from lithography to advanced packaging, operates from the same product data model. PLM engineers build and maintain that model, ensuring that when a process engineer in the etch module changes a recipe, the metrology team downstream sees the update in real time and the yield analytics system recalculates its baselines without a manual data export.
IT systems integration roles at ASML carry similar weight. Glassdoor lists 43 open positions for IT Engineer Systems Integration at the company, a figure that reflects the sheer number of machines and software platforms that must communicate inside a modern fab. ASML's own EUV lithography systems each generate terabytes of operational data per day. Multiply that by the hundreds of tools in a full-scale facility, layer on automated material handling systems, in-line metrology, and AI-driven process control, and the integration challenge becomes clear: someone has to architect the network, manage the data pipelines, and keep the whole system running when a single dropped connection can halt wafer production and cost millions.
Tesla's own hiring for Terafab reinforces the pattern. The company posted a Silicon Module Process Engineer role spanning lithography, etch, deposition, epitaxy, metals, implant, polish, and metrology, a list that reads like a map of the entire semiconductor process flow. The Technical Program Manager role Tesla is recruiting for explicitly calls for someone who can coordinate across semiconductor physicists, civil engineers, automation specialists, and business stakeholders. That is not a manufacturing job in the traditional sense. It is a systems integration job that happens to take place in a factory.
The automation layer ties it all together. A facility targeting one million wafer starts per month, Musk's stated long-term goal for the full-scale Terafab, cannot rely on human operators to move wafers between process steps. Automated material handling systems, robotic transfer arms, and AI-driven scheduling algorithms must orchestrate the flow of thousands of wafers through hundreds of process steps with cycle times measured in hours. The engineers who design and maintain these systems sit at the intersection of mechanical engineering, software development, and semiconductor process knowledge. They are among the hardest roles to fill because the talent pool that understands all three domains is vanishingly small.
What the hiring data makes plain is that the bottleneck in building Terafab is not the lithography machines, ASML already makes those. It is the people who can wire a city-sized factory into a coherent, data-driven system. Every PLM engineer, IT architect, and automation specialist ASML and Tesla brings on board is a signal that the project is moving from announcement into execution, and that the real competition is not over equipment contracts but over the engineers who can make the equipment work together.
The Talent War Nobody Is Talking About
ASML's hiring push for Terafab isn't happening in a vacuum. It's one front in a global semiconductor talent war that governments, chipmakers, and equipment suppliers are all losing, and the numbers behind it are staggering.
Deloitte estimates that the semiconductor industry will need more than one million additional skilled workers by 2030, roughly 100,000 per year. That figure sounded alarming when Deloitte first published it. Two years later, it looks optimistic. The US CHIPS Act has committed $39 billion in direct incentives, and as of July 2025, the Department of Commerce had awarded funding to 19 companies across 40 projects, from TSMC's $11.6 billion package for three Arizona fabs to Intel's $7.9 billion spread across six sites. The GAO's December 2025 report on those awards shows the projects span every stage of the supply chain, from leading-edge logic to materials production, with completion milestones stretching to 2033.
Each of those projects needs people. Deloitte's workforce analysis found that the US alone would need to grow its semiconductor workforce at a pace that outstrips the pipeline of relevant graduate students, fewer than 100,000 are enrolled annually in electrical engineering and computer science programs across the country. And that's before accounting for the specialized skills that modern fabs demand: not just process engineers and lithography specialists, but PLM architects, IT infrastructure leads, and automation engineers who can bridge the gap between equipment and production software.
The problem is structural, not cyclical. In 2021, the global semiconductor industry employed roughly two million people directly and generated about $275,000 in revenue per worker. That productivity figure was possible because manufacturing was intensely clustered, 80% of chips made in four East Asian countries, over 90% of assembly, testing, and packaging concentrated in the same region. The CHIPS Act and the EU Chips Act are deliberately breaking that concentration. The US wants to go from 10% of global chip manufacturing in 2022 to 30% by 2030. The EU wants to double its share to 20%. Combined, regions that produce about a fifth of the world's chips today want to make half by decade's end.
That geographic diversification is good for supply chain resilience. It's brutal for labor efficiency. Spreading production across more locations means companies need more people in more places to produce the same output, and the talent doesn't exist locally in most of those places. Of the nearly 500 assembly and test facilities worldwide, only 65 are in the Americas and 24 in Europe. If the US and Europe want true end-to-end self-sufficiency, not just fabs that ship wafers to Asia for packaging, they need to grow their back-end workforce even faster than their manufacturing workforce.
Samsung's experience at its Taylor, Texas fab illustrates the scarcity. The company entered ramp-up phase with a massive hiring push, and more than half the open roles targeted engineers with 2nm process experience. That expertise effectively exists at three companies on Earth: Samsung itself, TSMC, and Intel. Samsung couldn't hire locally. Nobody can.
This is the context that makes ASML's Terafab hiring significant beyond the headline number of roles. ASML isn't just filling positions for one project. It's competing for a finite pool of PLM engineers, automation specialists, and IT architects against Intel's Ohio expansion, TSMC's Arizona build-out, Micron's New York and Idaho fabs, and Samsung's Texas operations, all ramping simultaneously, all drawing from the same shallow talent pool. Accenture's 2025 report on the semiconductor talent shortage frames it as an ecosystem problem: for fabs and R&D centers to be operational, companies need to build talent pipelines from the ground up, in some cases in regions that have never had a semiconductor workforce.
Global chip sales are projected to hit $975 billion in 2026, with AI chips alone approaching $500 billion in revenue. But AI chips represent less than 0.2% of total unit volume, the value is concentrated in a tiny number of highly complex wafers. That means the industry's revenue growth is riding on the most talent-intensive segment of the business: leading-edge logic and advanced packaging, exactly the areas where ASML's EUV and High-NA EUV tools are essential, and exactly where the talent shortage is most acute.
The competition isn't just between chipmakers. It's between every sector that needs semiconductors and every government that views chip sovereignty as a national security priority. ASML sits at the chokepoint, it's the sole supplier of EUV lithography machines, the technology that makes leading-edge chips possible. When Terafab or any other advanced fab project ramps, ASML's customer support engineers, field service technicians, and training staff are the bottleneck between a finished building and a production line that actually works.
Why Musk's Space Ambitions Need ASML
The Terafab announcement didn't come from nowhere. It came from a straightforward problem: Musk's companies are running out of compute.
In January 2026, SpaceX filed an FCC application for a constellation of up to one million orbital datacenter satellites, the largest satellite constellation ever proposed, by an order of magnitude. The plan, developed in partnership with xAI, is to build a distributed AI inference network in low-Earth orbit that processes data from autonomous vehicles, drones, and defense assets in near-real-time, bypassing the latency of ground-based cloud computing. Off Earth Data reported that 80% of Terafab's output is earmarked for these orbital satellites, with the remaining 20% split between Tesla vehicles and the Optimus humanoid robot.
Musk said Terafab would produce enough chips to support 100 to 200 gigawatts of computing power per year on Earth, plus a terawatt in space.
What makes this a vertical-integration play rather than a procurement problem is the nature of the chips themselves. SpaceX needs radiation-hardened, power-efficient processors that can survive thermal cycling between -150°C and +150°C per orbit, constant radiation exposure, and the absence of convective cooling. Commercial chips fail within hours in those conditions. Tesla needs edge-inference processors that can deliver more than 1,000 TOPS while drawing under 100 watts for the Cybercab robotaxi and Optimus. Neither requirement maps to off-the-shelf silicon from Nvidia or AMD.
"We either build the Terafab or we don't have the chips," Musk said in Austin. "We need the chips, so we're going to build the Terafab."
This is where ASML enters the picture, and why the company matters more to engineers outside semiconductors than most realize. Terafab, or any facility aiming to produce chips at the 2nm or 3nm nodes that these applications demand, cannot fabricate logic chips without extreme ultraviolet lithography. ASML is the sole supplier of EUV machines in the world.
The dependency runs deeper than a single tool order. ASML's High-NA EUV systems, the EXE:5000 and its successor EXE:5200B, are the gateway to the next generation of process nodes. The company shipped its first High-NA tool in late 2023 and delivered the 5200B in late 2025, rated at 175 wafers per hour. As Terafab ramps toward production, the demand for ASML's most advanced systems will intensify, not just from the Musk venture but from Intel, TSMC, and Samsung, all of whom are racing to secure allocation.
The feedback loop is self-reinforcing. SpaceX's satellite constellation needs custom chips. Custom chips need advanced lithography. Advanced lithography needs ASML. And ASML's capacity to deliver those systems, which means hiring the engineers, manufacturing technicians, and field service specialists who build and maintain them, becomes the bottleneck that determines whether Musk's orbital compute vision stays on the drawing board or reaches orbit.
Intel's April 2026 decision to sign on as Terafab's primary foundry partner adds another layer. Tan has staked his turnaround strategy on Intel Foundry Services, and Terafab gives the company the anchor customer it needs to justify its $28 billion Ohio mega-fab and its CHIPS Act subsidies. But Intel's 18A process node, the one Terafab would depend on, still needs to prove high-volume manufacturing yields. If it slips, the pressure on ASML to deliver next-generation tools on schedule only increases.
Musk's empire is, in effect, building a closed-loop compute ecosystem: SpaceX provides launch capacity and orbital infrastructure, xAI provides the AI models and compute demand, Tesla provides capital markets access and manufacturing experience from its chip program, and Intel provides the foundry backbone. ASML sits beneath all of it, supplying the machines that make the silicon possible.
Whether Terafab hits its targets is an open question. Tesla's CFO confirmed the $25 billion cost isn't in Tesla's 2026 capital expenditure plan. No construction timeline has been announced. Sam Altman called orbital datacenters "ridiculous" in February 2026.
But the strategic logic is hard to dismiss. SpaceX controls the majority of global commercial launch. It has over 6,000 Starlink satellites already in orbit. xAI operates the Colossus cluster in Memphis. Tesla ships millions of vehicles a year. No other entity on Earth controls all three legs of the stool: launch, compute demand, and manufacturing scale.
For engineers watching this space, the implication is less about whether Terafab succeeds and more about what it signals: the bottleneck for the next decade of AI and space computing isn't algorithms or rocket engines. It's the machines that print transistors onto silicon, and the thin global workforce that builds and operates them.
What Engineers and Operators Should Watch Next
The hiring signals are already visible for anyone tracking where semiconductor talent demand is heading. Engineering roles across the US chip sector are projected to grow 15% by 2025, according to Talenbrium's hiring trends forecast. The Data/AI cluster is expected to see even steeper growth, a 25% jump in openings, as fabs lean on machine learning for yield optimization and predictive maintenance. For engineers weighing their next move, those numbers suggest the window to enter or pivot into this space is still widening, but the specialization bar is climbing.
SpaceX added 98 roles in the past week alone, including software engineers for its Raptor engine program in Hawthorne and operations engineers for Starship. The range tells you something: this isn't just a US story. The work is distributed across ASML's global support network, and engineers willing to locate near fabs, in the Netherlands, the American Southwest, or East Asia, will find more leverage.
Geography matters. The Brainport region in North Brabant, anchored by TU Eindhoven, the High Tech Campus, and the triple-helix model linking industry, academia, and government, remains the densest concentration of semiconductor talent in Europe. The Dutch government's National Microchip Talent Strengthening Plan has committed to backing that ecosystem with housing investment and labor migration policy, including the 30% tax ruling for highly skilled migrants, though Fragomen reports that the new coalition government is tightening compliance for sponsors of those migrants in 2026. Engineers eyeing a move to the Netherlands should watch those policy shifts closely; the door is open but the terms are changing.
On the skills side, Talenbrium estimates that 45% of tasks in semiconductor manufacturing and design could be automated by 2030 through advances in robotics, AI, and machine learning. That doesn't mean 45% of jobs disappear, it means the jobs that remain will sit closer to the intersection of domain knowledge and software fluency. PLM engineers who can write scripts, IT architects who understand process control loops, and automation specialists who can operate across both the digital and physical layers of a fab will be the ones most in demand. The Terafab-scale projects now underway will define what those hybrid roles look like in practice.
The companies hiring now, ASML, SpaceX, and the broader equipment and automation stack behind them, are defining job categories that didn't exist five years ago. Waiting until the roles are standardized means competing with everyone else who had the same idea.
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