Job Description
Introduction to the job
As an FPGA design scientist, you will participate in a cross-functional and collaborative team to specify and create custom digital circuit designs, simulate, implement and support hardware testing for future ASML’s EUV Source with a strong focus on real‑time control, diagnostics, and system‑level FPGA solutions envisioned in production EUV source platforms. You will be contributing in a research environment that strongly emphasizes on novel, innovative ideas to the N+3 generation of EUV source product, while delivering robust, testable FPGA implementations that also bridge advanced concepts into deployable EUV source firmware for current and next‑generation systems (N+1 / N+2).
Role and responsibilities
Responsible for contributing to, and translating requirements, into qualified firmware design solutions, with a focus on innovation and out-of-the-box thinking.
Define and execute RTL design and implementation, verification, block-level simulations, hardware integration / test throughout the FPGA development process from ideation through volume release.
Collaborate with a team of FPGA engineers to realize the solution, including deliverables tracking and peer-reviewing HDL output, from early architecture trade-offs through lab test setups, system integration, and volume-release readiness.
Documentation of design solution using standardized templates and guidelines.
Collaborate in a complex and fast-paced environment with FPGA design, verification and test engineers as well as adjacent engineering competencies such as software and control engineering.
Continually sharpen technical and professional skill-sets through available development programs.
Other duties as assigned with subject to change as required at any time.
Education and experience
MS or higher in EE, CS or related engineering fields.
Minimum of eight (8) years of experience in FPGA design with demonstrated success in full FPGA development cycles; requirement decomposition through realization.
Demonstrated expertise and experience in FPGA design (VHDL) and Module / Multi-Module verification (System Verilog). Experience with automated self-checking test bench verification and using UVM framework a plus, with emphasis on deterministic, safety‑critical, and high‑reliability designs used in real‑time EUV source operation.
Ability to complete timing simulation/post route simulation and static timing analysis.
Strong experience in hardware development tools and IDE for Xilinx devices; additional experience in Altera development tools a plus.
Ability to utilize lab hardware and IDE cores to debug (ILAs, VIO, SignalTaps, etc.)
Familiar with SoC, bus topology, AXI, PCIe, PTP, TSN, SRIO and associated IP.
Familiar with configuration management/version control/build automation.
Skills
Able to abstract requirements into concept and solution space
Ability to learn and apply new information and/or skills.
Demonstrated creative problem solving for complex issues.
Can read and interpret data, information, and documents.
Track record of completing assignments with attention to detail and high degree of accuracy.
Proven ability to perform effectively in a demanding environment, within provided timelines, and with changing workloads.
Results driven; exhibits ownership and accountability.
Work independently or as part of a team and follow through on assignments with minimal supervision.
Strong professional communication which is clear and concise.
Ability to establish and maintain cooperative working relationships with co-workers.
Other information
This position is located on-site in San Diego, California. It requires onsite presence to attend in-person work-related events, trainings and meetings and to further ensure teamwork, collaboration and innovation.
Routinely required to sit; walk; talk; hear; use hands to keyboard, finger, handle, and feel; stoop, kneel, crouch, twist, reach, and stretch. Occasionally required to move around the campus.
Occasionally lift and/or move up to 20 pounds.
Specific vision abilities required by this job include close vision, color vision, peripheral vision, depth perception, and ability to adjust focus.
Must be willing to work in a clean room environment, wearing coveralls, hoods, booties, safety glasses and gloves for entire duration of shift.
While performing the duties of this job, the employee routinely is required to sit; walk; talk; hear; use hands to keyboard, finger, handle, and feel; stoop, kneel, crouch, twist, reach, and stretch.This position requires access to controlled technology, as defined in the Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require the Company to proceed with candidates who are immediately eligible to access controlled technology.
The current base annual salary range for this role is currently:
$0-0Pay scales are determined by role, level, location and alignment with market data. Individual pay is determined through interviews and an assessment of several factors that that are unique to each candidate, including but not limited to job-related skills, relevant education and experience, certifications, abilities of the candidate and pay relative to other team members.
The Company offers employees and their families, medical, dental, vision, and basic life insurance. Employees are able to participate in the Company’s 401k plan. Employees will also receive eight (8) hours of vacation leave every month and (13) paid holidays throughout the calendar year. For more information, please contact the Recruiter or click on this link Compensation & Benefits in the US.
All new ASML jobs have a minimum application deadline of 10 days.
This position requires access to controlled technology, as defined in the United States Export Administration Regulations (15 C.F.R. § 730, et seq.). Qualified candidates must be legally authorized to access such controlled technology prior to beginning work. Business demands may require ASML to proceed with candidates who are immediately eligible to access controlled technology.
Inclusion and diversity
ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that inclusion and diversity is a driving force in the success of our company.
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Request an Accommodation
ASML provides reasonable accommodations to applicants for ASML employment and ASML employees with disabilities. An accommodation is a change in work rules, facilities, or conditions which enable an individual with a disability to apply for a job, perform the essential functions of a job, and/or enjoy equal access to the benefits and privileges of employment. If you are in need of an accommodation to complete an application, participate in an interview, or otherwise participate in the employee pre-selection process, please send an email to USHR_Accommodation@asml.com to initiate the company’s reasonable accommodation process.
Please note: This email address is solely intended to provide a method for applicants to initiate ASML’s process to request accommodation(s). Any recruitment questions should be directed to the designated Talent Acquisition member for the position.
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Job Details
- Category
- Avionics
- Employment Type
- Full Time
- Location
- San Diego, CA, USA
- Posted
- Mar 29, 2026, 08:00 PM
- Listed
- Mar 30, 2026, 06:39 PM
About ASML
Part of the growing space & AI ecosystem pushing the frontiers of technology.
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