# Physical Design and Verification Engineer **Company:** [Neuralink](https://zerogtalent.com/frontier-companies/neuralink) **Location:** South San Francisco, California, United States **Work mode:** On-site **Seniority:** Senior **Employment type:** Full Time **Salary:** USD 131K–265K/yr **Category:** Electrical **Department:** Other **Listed:** 2026-11-05 [View and apply on Zero G Talent](https://zerogtalent.com/frontier-jobs/neuralink/physical-design-and-verification-engineer-8197036003) ## What you'll do - Own block-to-full-chip implementation and signoff on 3DIC products - Lead multi-physics verification for stacked-die and chiplet systems - Define hierarchical partitioning and floorplans for large SoCs - Manage die-to-die partitioning and inter-die floorplan alignment - Drive STA, DRC/LVS, and EM/IR signoff across all corners ## What you need - 5+ yrs physical design experience on advanced nodes - Full-cycle RTL-to-GDSII on 7nm/5nm/4nm/3nm - Hierarchical top-level implementation on multi-million instance designs - STA and physical verification signoff expertise - Proficiency with Cadence, Synopsys, and Siemens signoff tools ## Job description **About Neuralink:** We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. **About the Role** We are seeking a Senior Physical Design Engineer to own block-to-full-chip implementation and signoff on advanced-node, multi-die 3DIC products. You will drive hierarchical physical design from RTL handoff through tapeout, and lead the multi-physics verification (thermal, mechanical/warpage, and IR/EM) that is unique to stacked-die and chiplet-based systems. This role sits at the intersection of traditional block-level signoff and the emerging discipline of 3D system-level closure. **Key Responsibilities** **Hierarchical Physical Design** - Define and execute the hierarchical partitioning strategy: block boundaries, feedthroughs, pin placement, and budgeting across levels of hierarchy. - Develop and maintain floorplans, power grids, and timing/physical budgets for large multi-block SoCs. - Own the interface between block owners and top-level integration, including abstract (ILM/ETM) generation, boundary timing, and hierarchical ECO propagation. - Manage die-to-die partitioning for 3D stacks – assign logic to tiers, plan hybrid-bond / µbump / TSV interfaces, and align inter-die floorplans. **Block-level Implementation & Signoff** - Synthesis: Drive logic synthesis (constraints, DFT insertion, physical-aware synthesis), QoR analysis, and RTL-to-gate correlation. - Floorplanning: Macro placement, power planning, congestion and timing feasibility, and pin/port optimization. - Placement & Optimization: Standard-cell placement, timing-driven and congestion-driven optimization, useful-skew and multi-corner/multi-mode closure. - CTS: Clock tree synthesis and clock distribution (including inter-die clocking for 3D), skew/latency balancing, and OCV/AOCV/POCV-aware clock closure. - Routing: Detailed routing, DRC/LVS convergence, signal integrity (crosstalk) closure, and antenna/via optimization. - Signoff: Static timing analysis (STA) across all corners/modes, physical verification (DRC/LVS/DFM), EM/IR (static and dynamic), and formal netlist equivalence. **3DIC Multi-Physics Verification** - Thermal: Build and run thermal models for stacked dies; analyze junction temperatures, hotspot coupling between tiers, and thermal-aware placement; feed thermal gradients back into timing and reliability signoff. - Mechanical: Perform warpage, stress, and CTE-mismatch analysis for stacked/bonded assemblies; validate bump/TSV/hybrid-bond mechanical integrity and assembly-induced reliability risks. - IR / Power Integrity: Static and dynamic IR-drop analysis across the 3D power delivery network, including inter-die PDN, TSV/bump resistance, decap strategy, and package-aware PI closure. - Correlate thermal, mechanical, and electrical effects such as thermal-induced timing derates and stress-induced device shifts into a coherent 3D signoff methodology. **Methodology & Collaboration** - Develop, document, and automate PnR and signoff flows (scripting, regression, QoR tracking). - Partner with packaging, design, DFT, DV, and CAD teams to align die/package/system co-design. - Debug convergence issues and drive root-cause analysis across timing, physical, and multi-physics domains. **Required Qualifications** - BS/MS in Electrical/Computer Engineering (or equivalent) with 5+ years of physical design experience; MS preferred. - Proven full-cycle RTL-to-GDSII experience on advanced nodes (7nm/5nm/4nm/3nm or comparable). - Hands-on hierarchical/top-level implementation on large (multi-million instance) designs. - Strong command of STA concepts (setup/hold, OCV/AOCV/POCV, MMMC) and physical verification signoff. - Proficiency with industry PnR and signoff tools (e.g., Cadence Innovus/Genus/Tempus/Voltus, Synopsys ICC2/Fusion Compiler/PrimeTime/StarRC, Siemens Calibre) and TCL scripting. **Preferred / Differentiating Qualifications** - Direct experience with 3DIC / 2.5D / chiplet implementation: TSVs, µbumps, hybrid bonding, interposers. - Multi-physics analysis experience with tools such as Ansys RedHawk-SC, Cadence Voltus/Celsius/Integrity 3D-IC, or Synopsys 3DIC Compiler. - Familiarity with thermal-aware and stress-aware design closure and die/package co-analysis. - Python/scripting for flow automation and data analysis; experience with regression/QoR frameworks. - Knowledge of reliability signoff (EM, aging/self-heat, ESD) in a 3D context. **Expected Compensation:** The anticipated base salary for this position is expected to be within the following range. Your actual base pay will be determined by your job-related skills, experience, and relevant education or training. We also believe in aligning our employees’ success with the company's long-term growth. As such, in addition to base salary, Neuralink offers equity compensation (in the form of Restricted Stock Units (RSU)) for all full-time employees. Base Salary Range: $131,000—$265,000 USD **What We Offer:** Full-time employees are eligible for the following benefits listed below. - An opportunity to change the world and work with some of the smartest and most talented experts from different fields - Growth potential; we rapidly advance team members who have an outsized impact - Excellent medical, dental, and vision insurance through a PPO plan - Paid holidays - Commuter benefits - Meals provided - Equity (RSUs) _\*Temporary Employees & Interns excluded_ - 401(k) plan _\*Interns initially excluded until they work 1,000 hours_ - Parental leave _\*Temporary Employees & Interns excluded_ - Flexible time off _\*Temporary Employees & Interns excluded_ ## Other open roles at Neuralink - [Veterinary Technician](https://zerogtalent.com/frontier-jobs/neuralink/veterinary-technician-8197226003) — Austin, Texas, United States - [Mechanical Design Engineer](https://zerogtalent.com/frontier-jobs/neuralink/mechanical-design-engineer-8196930003) — Austin, Texas, United States - [Manufacturing Material Coordinator](https://zerogtalent.com/frontier-jobs/neuralink/manufacturing-material-coordinator-8107986003) — Austin, Texas, United States - [Software Engineer, Hippocampus](https://zerogtalent.com/frontier-jobs/neuralink/software-engineer-hippocampus-6521585003) — Austin, Texas, United States - [Infrastructure Engineer, Mechanical Tooling](https://zerogtalent.com/frontier-jobs/neuralink/infrastructure-engineer-mechanical-tooling-8044955003) — Austin, Texas, United States; South San Francisco, California, United States --- *Source: [Zero G Talent](https://zerogtalent.com), the job board for space, defense, AI, robotics and frontier-tech companies.*