SpaceX Already Makes 85% of Its Launch Hardware In-House. Now It's Doing the Same Thing to the Silicon Inside Its Dishes.
SpaceX's Bastrop, Texas campus is installing equipment at an advanced chip packaging facility targeting in-house RF chip production by the end of 2026 — a move that would close the last major custom-silicon gap in every Starlink terminal and create a category of hardware roles that barely existed in the commercial space industry five years ago. The company that already produces roughly 85% of its launch hardware in-house is now applying the same vertical integration playbook to the silicon inside its dishes, and the ripple effects are reshaping hiring for RF and analog chip designers across Texas.
Zero G Talent's job board lists 141 SpaceX roles added in the past seven days, including a PCB Designer position at the Bastrop campus and multiple production technician roles supporting Starlink operations in Washington state. The volume alone signals a company in aggressive expansion mode. But the roles that matter most for this story — RFIC designers, mixed-signal engineers, antenna-on-chip specialists — are the ones that don't show up in simple job-board counts because they're being filled through targeted recruiting, not broad postings.
From Dish Factory to Silicon Campus
The Bastrop facility's physical expansion tells the story of Starlink's strategic evolution more clearly than any earnings call. It is transforming from a satellite terminal assembly plant into a vertically integrated semiconductor campus.
The original 541,000-square-foot facility began operations in January 2024 and doubled to approximately 1.2 million square feet by year's end — a pace of construction that mirrored SpaceX's characteristic urgency. The current expansion adds 1 million more square feet, bringing the total to over 1.7 million. That footprint will house not only Starlink kit production lines but also advanced silicon products, printed circuit boards, a semiconductor failure analysis lab, and panel-level packaging operations.
Construction on initial phases began in late 2024, with portions nearing completion by early 2025 and full build-out continuing into 2026 and 2027. Governor Greg Abbott has publicly framed the project as central to Texas's semiconductor ambitions, projecting more than $280 million in investment over three years. The state backed that projection with a $17.3 million grant from the Texas Semiconductor Innovation Fund — SpaceX's fifth from the program.
At 15,000 standard kits per day — a figure confirmed independently by both Senior Director of Starlink Production Alexandra Noe and Senior Director John Federspiel — Bastrop is already one of the highest-volume consumer electronics manufacturing sites in the United States. Non-standard units (premium kits, cruise ship terminals, Starlink Mini, aviation, and commercial variants) add another 25–35% on top. With the expansion, SpaceX projects capacity of 22,000–25,000 standard kits daily.
But the new square footage is not primarily for more dish assembly. It is for the silicon that goes inside them, and that distinction is what makes this expansion qualitatively different from anything SpaceX has built before.
The Chip Stack Inside Starlink — And Why SpaceX Wants to Own It
Starlink V3 terminals already rely on three distinct in-house custom chips, but the RF modules that handle low-noise amplification and high-power transmission are still sourced externally. Closing that gap is the entire point of the Bastrop chip packaging facility.
The V3 terminal's chip architecture reveals how far SpaceX has already pushed into custom silicon. The digital beamformer, called Shiraz V3, is a SpaceX-designed chip that handles the phased-array beam steering essential to Starlink's performance. A calibration controller tied to the Catson/Catapult chip family manages antenna tuning and signal integrity. The RF modules — responsible for the critical front-end functions of amplifying weak incoming signals and boosting outgoing transmissions — remain the domain of external suppliers.
This is the gap the Bastrop packaging facility is designed to close. By bringing RF chip packaging in-house, SpaceX eliminates a dependency that sits at the most performance-sensitive layer of the terminal's architecture. The facility is already installing equipment, targeting production start by the end of 2026, though the project has experienced some delays.
External partners still play a role. Xsight Labs, a fabless semiconductor firm, has partnered with SpaceX to supply switch and DPU chips for future non-terrestrial networks. Wistron NeWeb Corporation invested $90 million across 2021 and 2023 to build and expand a 28-acre Starlink component facility in Vietnam's Ha Nam Province. But the trajectory is clear: the highest-value, most differentiated silicon moves in-house first.
RFIC, Mixed-Signal, and Antenna-on-Chip Roles That Didn't Exist in Space Five Years Ago
SpaceX's semiconductor push is creating a new category of hardware roles in Texas. RFIC designers, mixed-signal engineers, and antenna-on-chip specialists are being recruited from Qualcomm, Apple, and defense primes at salaries well above market averages for comparable positions.
The roles themselves are distinctive. RFIC design for satellite communications terminals requires expertise that sits at the intersection of wireless communications, semiconductor physics, and antenna theory — a combination that has traditionally lived in defense contractors and wireless infrastructure companies, not in space companies. Mixed-signal design for beamformer calibration and antenna-on-chip integration for phased arrays are even more specialized.
Five years ago, these roles effectively did not exist in the commercial space industry. Space companies bought RF modules from established suppliers and focused their engineering talent on systems integration, orbital mechanics, and launch vehicle design. SpaceX's vertical integration strategy has collapsed that boundary, creating demand for chip designers who understand both silicon and satellite communications — a profile that is rare enough to command the premiums SpaceX is paying.
The sourcing pattern is telling. SpaceX is not training from scratch but recruiting directly from companies where this expertise already lives: Qualcomm's wireless chip divisions, Apple's custom silicon teams, and defense primes with classified RF programs. This poaching strategy signals urgency and a willingness to compress years of hiring into months.
Why SpaceX Chose Bastrop
SpaceX's choice of Bastrop is not accidental. It sits at the intersection of Texas's aggressive semiconductor incentive strategy and the company's need for a talent pipeline that connects to Austin's chip design ecosystem.
The $17.3 million Texas Semiconductor Innovation Fund grant is a meaningful accelerant for the Bastrop expansion, but it is also a signal of alignment between the company's ambitions and the state's economic development strategy. Texas has positioned itself as a domestic semiconductor manufacturing hub, competing with Arizona, Ohio, and New York for fab investments, and SpaceX's Bastrop campus is one of the highest-profile commitments in that competition.
The location, 33 miles southeast of Austin, places the facility within commuting distance of the city's deep chip design talent pool — a pool built over decades by companies including AMD, NXP, Silicon Labs, and numerous Apple and Samsung design centers. For RF and mixed-signal engineers considering a move into space hardware, the Austin corridor offers a familiar professional ecosystem with a novel mission.
The Bastrop facility's progressive build-out timeline — initial phases nearing completion by early 2025, full build-out continuing into 2026 and 2027 — mirrors the phased nature of the hiring push. SpaceX is not waiting for the building to be finished to start recruiting; the roles are being filled in parallel with construction, which is consistent with the company's pattern of compressing development timelines across all its programs.
What Comes After Packaging
The Bastrop packaging facility is only the visible layer of SpaceX's semiconductor ambitions in Texas. Plans for a fabrication facility in Grimes County and the Terafab AI compute project in Austin suggest that in-house chip packaging is a stepping stone toward something much larger.
SpaceX has filed plans for a semiconductor fabrication facility in Grimes County, Texas, described as a "vertically integrated semiconductor manufacturing and advanced computing fabrication facility." One estimate puts the total investment potentially reaching $119 billion, though details remain thin. At that scale, the project would represent one of the largest private industrial investments in American history. The filing itself signals that SpaceX's leadership views semiconductor fabrication as a strategic necessity, not an experiment.
Elon Musk announced plans in March 2026 for advanced chip factories in Austin, Texas, as part of a broader push to strengthen in-house semiconductor capabilities. The Terafab project — a joint SpaceX and Tesla initiative targeting over one terawatt of AI compute capacity per year, valued at up to $25 billion — adds another dimension. Intel's April 2026 announcement that it would contribute manufacturing expertise, including its 14-angstrom process technology, to Terafab suggests that SpaceX is building partnerships to accelerate its semiconductor learning curve even as it develops in-house capabilities.
For the RF and mixed-signal engineers being hired today, the implication is significant. The roles being filled at Bastrop in 2025 and 2026 are likely to evolve as the company moves from packaging to fabrication. Engineers who enter now will have the opportunity to shape process design, yield optimization, and chip architecture at a company that has historically rewarded early employees with outsized equity and responsibility.
Why Mid-Career Chip Designers Should Pay Attention Now
The convergence of SpaceX's hiring urgency, the novelty of these roles in the space industry, and the equity compensation structure creates a narrow window for mid-career RF and analog chip designers to enter space hardware at a ground-floor moment — before the roles professionalize, the hiring wave saturates, and the equity upside compresses.
SpaceX's compensation model has historically been front-loaded in equity relative to base salary. For engineers coming from Qualcomm or Apple, the base salary alone may not be the draw. The equity is.
But equity in a company at this stage of a strategic pivot carries a different risk-reward profile than equity in a mature semiconductor company. SpaceX remains privately held, and its valuation — already among the highest of any private company — reflects enormous expectations. The semiconductor vertical integration strategy is unproven at scale. The Bastrop packaging facility has not yet produced a chip, and the Grimes County fab is years from operation. The upside is that early employees in a successful vertical integration effort capture disproportionate value. The downside is that the strategy could stall, pivot, or be deprioritized.
The hiring window is narrow for a structural reason. Once SpaceX fills its initial cohort of RFIC and mixed-signal designers, the urgency will diminish. The company's pattern across other engineering disciplines — from propulsion to avionics — is to hire aggressively during a capability-building phase and then shift to maintenance-level hiring. Mid-career designers who wait for the roles to be "proven" will find them filled and the equity diluted.
By the end of 2026, if SpaceX's timeline holds, the Bastrop facility will be packaging RF chips for Starlink terminals in a building that, two years earlier, was producing nothing but satellite dishes. The engineers who designed those chips will have done so in roles that did not exist in the space industry when they accepted their offers. The dishes on the roof were always just the beginning.
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